1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a capacitor having an improved structural stability and a method of manufacturing the capacitor.
2. Description of the Related Art
In general, semiconductor memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices can store data or information therein. The data or information is stored in the semiconductor memory devices, and also the data or information is read from the semiconductor memory devices. A typical single unit memory cell of the semiconductor memory device includes one capacitor and one transistor. The capacitor of the semiconductor memory device generally has a storage electrode, a dielectric layer, and a plate electrode. To improve the storage capacity of the semiconductor memory device, the capacitor needs a large capacitance.
As the degree of integration of the semiconductor memory device has increased, the unit memory cell of the semiconductor memory device has continuously decreased in area. To ensure a sufficient storage capacitance of the semiconductor memory device, the capacitor may have various shapes, such as a box, a fin, a crown, a cylinder, etc. However, due to design constraints of the semiconductor memory device that include size decreases, the capacitor should have an increasingly large aspect ratio, defined as the ratio of the height to the width of the capacitor. Thus the capacitor may have sufficient capacitance when formed in a limited unit area of the semiconductor memory device. As a result, however, the capacitors having a high aspect ratio may mechanically collapse so that a so-called two-bit failure may occur between adjacent capacitors.
FIG. 1 is a schematic cross-sectional view illustrating conventional cylindrical capacitors.
Referring to FIG. 1, a conventional capacitor includes a cylindrical storage electrode 13 connected to a contact pad 4 formed on a semiconductor substrate 1. The cylindrical storage electrode 13 is electrically connected to the contact pad 4 by a contact plug 10 formed in an insulation layer 7 that covers the semiconductor substrate 1. To increase the storage capacitance of the semiconductor memory device, the cylindrical storage electrode 13 of the capacitor has a greatly increased height. When the cylindrical storage electrode 13 has this greatly increased height, the cylindrical storage electrode 13 may collapse toward an adjacent cylindrical electrode so that adjacent capacitors may be inadvertently connected to each other. This is shown in FIG. 1 by dashed cylindrical storage electrode 13. The collapse of the cylindrical storage electrode 13 is referred to as a two-bit failure. When the two-bit failure occurs in the semiconductor memory device, the semiconductor memory device may not properly operate.
Accordingly, U.S. Patent Application Publication No. 2003/85420 discloses a semiconductor device including a beam-shaped insulating member between capacitors of the semiconductor device to improve the mechanical strength of the capacitor.
FIG. 2A is a cross-sectional view illustrating the semiconductor device including the beam-shaped insulating member, and FIG. 2B is a plan view illustrating the semiconductor device in FIG. 2A.
Referring to FIGS. 2A and 2B, after a semiconductor substrate 15 is divided into an active region and a field region by forming an isolation layer 18 on the semiconductor substrate 15, gate structures 27 are formed in the active region of the semiconductor substrate 15. Each of the gate structures 27 includes a gate oxide layer pattern, a gate electrode and a mask pattern.
Impurities are implanted into portions of the semiconductor substrate 15 by an ion implantation process using the gate structures 27 as masks, forming source/drain regions 21 and 24 at the portions of the substrate 15 between the gate structures 27. Thus, metal oxide semiconductor (MOS) transistors are formed on the semiconductor substrate 15.
After a first insulating interlayer 42 is formed on the substrate 15 to cover the MOS transistors, capacitor plugs 30 and a bit line plug 33 are formed through the first insulating interlayer 42. The capacitor plugs 30 and the bit line plug 33 are connected to the source/drain regions 21 and 24, respectively.
After a second insulating interlayer 45 is formed on the first insulating interlayer 42, the second insulating interlayer 45 is partially etched to form a bit line contact plug 36 making contact with the bit line plug 33.
A third insulating interlayer 48 is formed on the second insulating interlayer 45. The third and second insulating interlayers 48 and 45 are successively etched to form capacitor contact plugs 39 making contact with the capacitor plugs 30, respectively.
After an etch stop layer 51 is formed on the third insulating interlayer 48 and the capacitor contact plugs 39, holes 54 exposing the capacitor contact plugs 39 are formed through the etch stop layer 51. Cylindrical bottom electrodes 57 making contact with the capacitor contact plugs 39 are formed in the holes 54, respectively. Here, the cylindrical bottom electrodes 57 are electrically connected to the source/drain regions 21 and 24 by the capacitor contact plugs 39 and the capacitor plugs 30.
After beam-shaped insulating members 72 are formed between sidewalls of adjacent bottom electrodes 57, dielectric layers 60 and top electrodes 63 are successively formed on the bottom electrodes 57 to thereby form capacitors 66 on the semiconductor substrate 15.
An additional insulation layer 69 is formed over the substrate 15 to cover the capacitors 66. Since the beam-shaped insulating members 72 are formed between the sidewalls of the adjacent bottom electrodes 57, the mechanical strength of the capacitor 66 may be improved.
However, in the above-described semiconductor device, processes for manufacturing the semiconductor device are complicated because at least four beam-shaped insulating members 72 should be formed between the adjacent bottom electrodes 57 to improve the mechanical strength of the capacitor 66. Thus, manufacturing cost and manufacturing time for the semiconductor device is increased. Additionally, the manufacturing processes are more complicated because the capacitor 66 has a complex structure including the bottom electrode 57, the beam-shaped insulating members 72, the dielectric layer 60 and the top electrode 63 as shown in FIGS. 2A and 2B. Further, the additional insulation layer 69 may not be precisely formed between the capacitors 66 having the complex structure so that the capacitors 66 may be inadvertently electrically connected to an upper wiring formed on the capacitors 66. As a result, the processes for manufacturing the semiconductor device including the capacitor 66 having the complex structure may have poor throughput.